Backoff & Memory Provisioning: Adaptive Spinning, Custom Allocators, NUMA & Huge Pages
Two resources a lock-free ring buffer takes for granted: time and memory. Adaptive backoff for waiting well, and a pluggable allocator trait for NUMA placement and huge pages.
Compile-Time Leverage: Specialization, Branch & Arithmetic Hygiene, and Inlining
How const generics, zero-sized types, branch and arithmetic hygiene, and disciplined inlining hand the Rust compiler enough compile-time facts to make sizes immediate, unused features free, and redundant checks disappear in a lock-free SPSC ring buffer.
Zero-Copy on the Hot Path: Reserve/Commit and Fast-Path/Slow-Path Splitting
How a reserve/commit protocol eliminates per-item copies in a lock-free SPSC ring buffer, and how fast-path/slow-path splitting keeps the common case branch-predictable.
Amortizing Cross-Core Coordination: Cursor Caching and Batch Processing
How cursor caching and batch processing amortize the cost of cross-core coordination in a lock-free SPSC ring buffer, so cores touch shared atomics a fraction as often.
The Cross-Core Contract: Memory Ordering and Single-Writer State in Lock-Free Rust
How Release/Acquire ordering, Relaxed counters, and single-writer UnsafeCell state make lock-free Rust ring buffers correct and efficient.
Cache-Conscious Data Layout in Rust: Field Zoning, False Sharing, and the 128-Byte Rule
How to lay out a shared Rust struct by who-touches-what - zoning fields by write owner and frequency, then padding the cross-core ones to avoid false sharing and prefetcher-induced contention.
Architectural Decomposition: Remove Contention by Design
The opening post of a Low-Level Systems Design in Rust series, arguing that the biggest performance win is structural: replace a shared multi-producer cursor that serializes cores through cache-coherence traffic with one private single-writer SPSC ring per producer, converting quadratic writer contention into a cheap O(N) consumer sweep.
Scalar Replacement of Aggregates: How "Copy to Locals" Unlocks the Compiler
How copying a small aggregate into local variables exposes Scalar Replacement of Aggregates to LLVM, letting hot loops keep state in registers instead of repeatedly loading and storing through a pointer—illustrated with Zig/Rust reproductions and TigerBeetle's AEGIS-128L speedup.
Why x86 Zeroes a Register With `xor eax, eax`
A practical reference on why x86 zeroes a register with xor reg, reg - breaking down the size and dependency advantages over mov, CPU zeroing idiom recognition, and the subtle flags tradeoff, with real code examples and tradeoffs
Set-Associative Caches: Trading Global Optimality for Predictable Speed
How set-associative caches trade global eviction freedom for bounded, cache-line-friendly lookups, and how TigerBeetle's CacheMap and a SIMD search optimization (PR #3200) put that trade-off to work.